Custom Resolution Utility (CRU)

[TnF]

(01-17-2019 06:11 PM)ToastyX Wrote:  

(01-17-2019 07:34 AM)TnF Wrote:  Yes indeed, 240Mhz limit. As of yesterday i didn't know what pixel clock meant, either way i managed to get to 1080p 103hz with original clocks and 105hz with custom timings confirmed no frame skipping. I couldn't find a timing combination that was stable at 106mhz. Is there is a methodology with the timings? I did several tests where i found min values for all 6 timings (back porch, front porch, sync, both H and V), but i couldn't use a combination of mins without problems. Is there is a methodology to this?

With laptop panels, the minimum is usually limited by the blanking, which is front porch + sync width + back porch. The individual values don't matter as much.

Yes indeed from the data i gathered testing you are pretty much spot on - wish i knew this sooner it would save me lots of time

Quote:

(01-17-2019 07:34 AM)TnF Wrote:  I spend the whole day before calling it day to push to more than 105hz. The obvious thing however is that pesky 240mhz pixel clock limit which if removed it might be possible to push further these displays (assuming eDP is not maxed out at 240Mhz, is should be underspec since i'm already there).

Too bad you haven't developed an intel pixel clock patcher I think more people would want one especially after all the info and guides i found over your tool in laptop forums mainly here ( http://forum.notebookreview.com/threads/...us.802167/ ).

A patcher wouldn't make a difference. The patchers are for external monitors and have no effect on DisplayPort limits.

Can you explain why this is? This laptop can be configured with a 4K screen @ 60hz, and even 10 bit (8+2 dithering) depth. This approximately required 4x the bandwidth as there are as 4x as many pixels in my understanding. So theoretically the interface should be able to do 4x60=240hz (i know i don't calculate the timings here but it's to get my point through). If i were to guess the interface is the latest eDP v1.4b which has more than enough bandwidth to do 1080p@120hz for example. Isn't the pixel clock rate related to the bandwidth of the interface? Why there is a 240mhz limit? If it was different how come normal DP (which eDP is based of) can run past that limit and clock patcher is available? :/